`timescale 10ns / 1ns
module test_zl_2346_4();
	reg clk;  //输入时钟信号
	reg x;
	wire clk_div; //输出分频后的时钟信号

	
	initial //初始化
	begin 
		clk   = 0;
		x     = 1;
		#60000 //延时 
		x     = 0;
	end 
	
	always #1 clk = ~clk;
	
	zl_2346_4 divider(
		.x       (x),
		.clk     (clk),
		.clk_div (clk_div)
	);
endmodule 
		